1. Technical Field
The present invention relates to an electronic control unit that has an integrated circuit element and is mounted in, for example, a vehicle, and relates to a component test unit that performs in the product shipment stage a rationalized anomaly check associating mutually an anomaly check for the electronic control unit in actual operation with a component anomaly check for the integrated circuit element built in the electronic control unit.
2. Description of the Related Art
In an electronic control unit mounted in, for example, a vehicle that includes an input interface circuit connected to input sensors; an output interface circuit connected to electric loads; and at least one integrated circuit element connected with the input interface circuit and the output interface circuit, the electronic control unit performs during operation a check on connection states of wirings to the input sensors and the electric loads connected externally, and performs an anomaly check whether there is an error in the control constants and the control program stored in the internal RAM memory and the program memory, whereby reliability of the control unit is enhanced. According to, for example, Japanese Patent Application Laid-Open No. 2009-030543A “IN-VEHICLE ENGINE CONTROL DEVICE”, a microprocessor that constitutes a first integrated circuit element includes, as a start-up inspection means, an interruption check means for the major external wirings; a read/write check means for the RAM memory; and a code check means for the program memory, and includes, as an regular inspection means inspecting during operation, a code check means for a program-memory block whose number n is successively incremented; and an invert logic verification means for the RAM memory. Moreover, a monitoring and control circuit section that is a second integrated circuit element used concurrently with the first integrated circuit element monitors the operational state of the microprocessor by periodically sending questionnaire information to the microprocessor being in operation, to determine whether answer information obtained from the microprocessor agrees with corresponding correct information, and initializes and reboots the microprocessor when detecting an error. (See FIG. 1, paragraphs [0015] and [0017]; FIG. 2, paragraph [0021]; and FIG. 3, paragraphs [0030] and [0031].)
According to Japanese Patent Application Laid-Open No. 2012-181138A “SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN DEVICE AND DESIGN METHOD”, on the other hand, a scan test method is applied to a test for the integrated semiconductor circuit, in which a scan chain circuit is configured by connecting serially a plurality of flip-flops in the integrated circuit, and an internal signal indicating a result obtained by inputting a test pattern to the integrated circuit and operating it is transferred through the scan chain circuit and is output externally. Scan test methods are categorized into an external scan test method (external test method) and a compressed scan test method (compressed test method, internal test method, or self-test method). In an external scan test method, a test data is scanned in from a test device provided externally of the integrated semiconductor circuit element, and a scan-out signal obtained is analyzed and evaluated by the test device. In a compressed scan test method, a scan-in data is generated by a pseudorandom number generator in the integrated semiconductor circuit, and a scan-out signal obtained is compressed to be analyzed and evaluated in the integrated semiconductor circuit. The patent application JP2012-181138A discloses a test method for a semiconductor integrated circuit of low-power consumption type that halts input of the clock signal to an unoperated register during operation. In the method, a design device, which is a test device, provided externally of the semiconductor integrated circuit element performs an external test using an external scan test method and the scan chain circuits are divided into a plurality of segments and a segment to which the clock signal to be fed is selected by a random number generator provided internally of the semiconductor integrated circuit element so that no overcurrent is generated during the test. (See FIG. 1, paragraph [0017]; and FIG. 3, paragraph [0028].)
In contrast to the above, Japanese Patent Application Laid-Open No. 2000-266815A “ELECTRONIC SYSTEM WITH SELF-DIAGNOSTIC FUNCTION AND SIMULATION APPARATUS FOR ELECTRONIC SYSTEM” employs a compressed scan test method that allows determination of normality or non-normality of a to-be-tested circuit without connecting it to an external test device. The patent application JP2000-266815A discloses a system that includes a random number generation means storing a pseudorandom number pattern shifted by one bit from a pseudorandom number pattern generated by a pseudorandom number generator provided in the integrated circuit element when the pseudorandom number generator serially outputs the pseudorandom number pattern, and outputting data constituting the one-bit-shifted pseudorandom number pattern to the scan pass circuit (the same meaning of “scan chain circuit”) when a logic operation result of the tested circuit is parallelly input to the scan pass circuit. (See FIG. 1.)
In addition, the integrated circuit-element testing methods described in the patent applications JP2012-181138A and JP2000-266815A are explained in “SCAN TEST”, Electronic Design Automation (EDA) Technical Committee of Japan Electronics and Information Technology Industries Association, online EDA Glossary (revised edition), Nikkei Business Publications, Jan. 13, 2009 (URL:http://techon.nikkeibp.co.jp/article/WORD/20090107/163744/). The scan test is performed by a series of operations of scan-in and scan-out. Turning a scan enabling signal to, for example, “H” logic level of the enabling state permits a scan-in mode, in which a diagnostic pulse-train signal is scanned-in in synchronism with the clock signal and then diagnostic information is input to each flip-flop circuit that constitutes a shift register. Then, turning the scan enabling signal to “L” logic level of the disabling state permits a capture mode, in which outputs of the combination circuits for the diagnostic information are captured into the flip-flop circuits on input of the internal clock signal in the capture mode. Turning again the scan enabling signal to “H” logic level of the enabling state permits a scan-out mode, in which the information in the shift registers is sent out as a measurement pulse-train signal in synchronism with the clock signal. The diagnostic section determines whether the combination circuit performs a normal logic operation by comparing correct pulse-train information with the measurement pulse-train signal for the diagnostic pulse-train signal input in the scan-in mode.
The vehicle-mounted engine control unit according to the patent application JP2009-030543A executes a complex functional check on various combination for the microprocessor and the monitoring and control circuit section in the integrated circuit element at start of operation or during operation, whereby reliability of the vehicle-mounted engine control unit is enhanced. However, no detail checks are made individually on the various combination circuits, with the microprocessor and the monitoring and control circuit section being halted. In particular, it is difficult to perform quickly the detail checks within a limited permissible time at start of operation; therefore such detail checks have been unachieved. The test method according to the patent application JP2012-181138A is no other than an external scan test method in actuality although the random number generator incorporated in the integrated circuit element is jointly used, and the patent application JP2000-266815A employs the compressed scan test method using the random number generator incorporated in the integrated circuit element. However, the scan pass circuit (scan chain circuit) disclosed in either application is used as a detail check means dedicated to the shipment inspection in the final process of manufacturing the integrated circuit element. Therefore, a detail check for various combination circuits cannot be performed by making use of these scan pass circuits (scan chain circuits), with the integrated circuit element assembled into the actual electronic control unit.
A first object of the present invention is to provide an electronic control unit that is composed of inexpensive integral circuit elements and is able to be checked in detail for various combinations of the integrated circuit element built in the electronic control unit within a limited time immediately after start or stop of operation. A second object of the present invention is to provide a component test unit for an integrated circuit element in which part of a scan pass circuit (hereinafter referred to as a scan chain circuit) used in a component test for the integrated circuit element can also be used as a detailed check means for the inside of the integrated circuit element when the integrated circuit element is mounted in the electronic control unit.